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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 발행연도
- 2018.11
- 수록면
- 1,447 - 1,454 (8page)
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이 논문의 연구 히스토리 (2)
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초록· 키워드
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In this paper, the design of robust DSC-PLL(Delayed Signal Cancellation Phase Locked Loop) is proposed for coping with frequency variation. This method shows significant performance for detection of fundamental positive sequence component voltage when the grid voltage is polluted by grid unbalance and frequency variation. The feedback frequency estimation of DSC-PLL is tracking the drift in the phase by unbalance and frequency variation. The robust DSC PLL is to present the analysis on method and performance under frequency variations. These compensation algorithms can correct for discrepancies of changing the frequency within maximum 193[ms] and improve traditional DSC-PLL. Linear interpolation method is adopted to reduce the discretized errors in the digital implementation of the PLL. For verification of robust characteristic, PLL methods are implemented on FPGA with a discrete fixed point based. The proposed method is validated by both Matlab/Simulink and experimental results based on FPGA(XC7Z030).
목차
Abstract
1. 서론
2. DSC-PLL 기법
3. 시뮬레이션 및 실험
4. 결론
References
참고문헌 (13)
참고문헌 신청
D. W. P. Thomas and M. S. Woolfson, “Evaluation of frequency tracking methods”, IEEE Trans. Power Delivery, vol. 16, pp. 367-371, July 2001.
Digital PLL control for grid connected solar power system, KIEE Trans, pp. 562-568, Sept 2004.
S. K. Chung, “A phase tracking system for three phase utility interface inverters”, IEEE Trans, Power Electron., vol. 15, no. 3, pp. 431-438, May 2000.
“Grid harmonics and Voltage Unbalance Effect Elimination for Three-Phase PLL Grid Synchronization Algorithm”, Energy Conversion Congress and Exposition (ECCE), 2013 IEEE, Sept. 2013, pp. 3299-3304.
P. Rodiruez, J. Pou, J. Bergas, J. I. Candela, R. P. Burgo, and D. Boroyevinh, “Decoupled Doubled Synchronous Reference Frame PLL for Power Converters Control”, IEEE Trans. Power Electron., vol. 22, pp. 584-592, May 2007.
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